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1 ds05-11221-1e fujitsu semiconductor data sheet memory cmos 2 m 64 bits hyper page mode dram module mb8502e064ab-60/-70 buffered, 2 m 64 bits hyper page mode dram module, 5 v, 1-bank n description the fujitsu mb8502e064ab is a fully decoded, cmos dynamic random access memory (dram) module consisting of eight mb8117805a devices. the mb8502e064ab is optimized for those applications requiring high speed, high performance and large memory storage. the operation and electrical characteristics of the mb8502e064ab are the same as the mb8117805a which features hyper page mode (edo) operation. for ease of memory expansion, the mb8502e064ab is offered in an 168-pin dual in-line memory module package (dimm). n product line & features parameter mb8502e064ab-60 MB8502E064AB-70 ras access time 60 ns max. 70 ns max. random cycle time 104 ns min. 124 ns min. address access time 35 ns max. 40 ns max. cas access time 20 ns max. 22 ns max. hyper page mode cycle time 25 ns min. 30 ns min. power dissipation operating mode 6600 mw max. 6105 mw max. standby mode 440 mw max. 440 mw max. this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. conformed to 8-byte dimm jedec standard organization: 2,097,152 words 64 bits module size: 1.00 (height) 5.25 (length) 0.350 (thick) memory: mb8117805a (2 m 8, 2 k ref.), 8 pcs tis input buffers, 2 pcs tis input driver for buffered pd, 1 pc parallel presence detect 5.0 v + 10% supply voltage 2,048 refresh cycles / 32.8 ms hyper page operation (edo) ras -only refresh / cas -before-ras refresh package and ordering information: 168-pin dimm, order as mb8502e064ab- dg (dg = gold pad)
2 mb8502e064ab-60/-70 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit supply voltage v cc e0.5 to +7.0 v input voltage v in e0.5 to +7.0 v output voltage v out e0.5 to +7.0 v short circuit output current i out 50 ma power dissipation p d 10 w storage temperature t stg e55 to +125 c 168-pin plastic dimm (socket type) (mds-168p-p06)
3 mb8502e064ab-60/-70 fig. 1 e block diagram dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 cas i/o i/o i/o i/o we ras chip 0 dq 0 dq 1 dq 2 dq 3 oe a 0 a 1 to a 10 a 0 a 1 to a 10 b 0 sn74abt162244 (drivers, chip 8, 9) dq 36 dq 37 dq 38 dq 39 dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dq 32 dq 33 dq 34 dq 35 dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 i/o i/o i/o i/o cas i/o i/o i/o i/o we ra s chip 1 oe a 0 a 1 to a 10 i/o i/o i/o i/o cas i/o i/o i/o i/o we ras chip 2 oe a 0 a 1 to a 10 i/o i/o i/o i/o cas i/o i/o i/o i/o we ras chip 3 oe a 0 a 1 to a 10 i/o i/o i/o i/o cas i/o i/o i/o i/o we ras chip 4 oe a 0 i/o i/o i/o i/o cas i/o i/o i/o i/o we ras chip 5 oe a 0 i/o i/o i/o i/o cas i/o i/o i/o i/o we ras chip 6 oe a 0 i/o i/o i/o i/o cas i/o i/o i/o i/o we ras chip 7 oe a 0 i/o i/o i/o i/o sn74abt2244 (chip10) ras 0 cas 0 we 0 oe 0 cas 1 cas 2 cas 3 pde ras 2 cas 4 we 2 oe 2 cas 5 cas 6 cas 7 v cc v ss c 0 to c 9 c 0 to c 9 pd 1 to pd 8 v cc or v ss a 1 to a 10 a 1 to a 10 a 1 to a 10 a 1 to a 10
4 mb8502e064ab-60/-70 n pin assignments pin no. mb8502e064ab pin no. mb8502e064ab pin no. mb8502e064ab pin no. mb8502e064ab 1v ss 43 v ss 85 v ss 127 v ss 2dq 0 44 oe 286dq 32 128 n.c. 3dq 1 45 ras 287 dq 33 129 n.c. 4dq 2 46 cas 488 dq 34 130 cas 5 5dq 3 47 cas 689 dq 35 131 cas 7 6v cc 48 we 290 v cc 132 pde 7dq 4 49 v cc 91 dq 36 133 v cc 8dq 5 50 n.c. 92 dq 37 134 n.c. 9dq 6 51 n.c. 93 dq 38 135 n.c. 10 dq 7 52 dq 16 94 dq 39 136 dq 48 11 n.c. 53 dq 17 95 n.c. 137 dq 49 12 v ss 54 v ss 96 v ss 138 v ss 13 dq 8 55 dq 18 97 dq 40 139 dq 50 14 dq 9 56 dq 19 98 dq 41 140 dq 51 15 dq 10 57 dq 20 99 dq 42 141 dq 52 16 dq 11 58 dq 21 100 dq 43 142 dq 53 17 dq 12 59 v cc 101 dq 44 143 v cc 18 v cc 60 dq 22 102 v cc 144 dq 54 19 dq 13 61 n.c. 103 dq 45 145 n.c. 20 dq 14 62 n.c. 104 dq 46 146 n.c. 21 dq 15 63 n.c. 105 dq 47 147 n.c. 22 n.c. 64 n.c. 106 n.c. 148 n.c. 23 v ss 65 dq 23 107 v ss 149 dq 55 24 n.c. 66 n.c. 108 n.c. 150 n.c. 25 n.c. 67 dq 24 109 n.c. 151 dq 56 26 v cc 68 v ss 110 v cc 152 v ss 27 we 069dq 25 111 n.c. 153 dq 57 28 cas 070 dq 26 112 cas 1 154 dq 58 29 cas 271 dq 27 113 cas 3 155 dq 59 30 ras 072 dq 28 114 n.c. 156 dq 60 31 oe 073 v cc 115 n.c. 157 v cc 32 v ss 74 dq 29 116 v ss 158 dq 61 33 a 0 75 dq 30 117 a 1 159 dq 62 34 a 2 76 dq 31 118 a 3 160 dq 63 35 a 4 77 n.c. 119 a 5 161 n.c. 36 a 6 78 v ss 120 a 7 162 v ss 37 a 8 79 pd 1 121 a 9 163 pd 2 38 a 10 80 pd 3 122 n.c. 164 pd 4 39 n.c. 81 pd 5 123 n.c. 165 pd 6 40 v cc 82 pd 7 124 v cc 166 pd 8 41 n.c. 83 id 0 125 n.c. 167 id 1 42 n.c. 84 v cc 126 b 0 168 v cc
5 mb8502e064ab-60/-70 n pin descriptions n presence detect (pd) / id definition n capacitance (t a = 25 c, f = 1 mhz, v cc = +5.0 v) symbol function input/output pin count a 0 to a 10 , b 0 address input input 12 ras 0 and ras 2 row address strobe input 2 cas 0 to cas 7 column address strobe input 8 we 0 and we 2 write enable input 2 oe 0 and oe 2 output enable input 2 dq 0 to dq 63 data input / data output input /output 64 pd 1 to pd 8 presence detect output 8 id 0 and id 1 id bit output 2 pde presence detect enable input 1 v cc power supply ? 16 v ss ground ? 16 n.c. no connection ? 16 symbol mb8502e064ab-60 MB8502E064AB-70 description of pd / id pd 1 h h module density, dram organization and addressing; module density: 16 mb, number of bank: 1 bank module contguration: 2 m 64 mounted dram contguration: 2 m 8 dram address (row / column): 11/10 pd 2 ll pd 3 ll pd 4 hh pd 5 h h edo detection; hyper page mode: pd 5 = h pd 6 hl module speed; 60 ns: pd 6 = h, pd 7 = h 70 ns: pd 6 = l, pd 7 = h pd 7 hh pd 8 h h ecc/parity detection; (parity): pd 8 = h id 0 l l module type; 64 (parity): id 0 = l id 1 h h refresh mode; self refresh: id 1 = h parameter symbol max. unit input capacitance, address c in1 20 pf input capacitance, ras c in2 50 pf input capacitance, cas , we , oe c in3 20 pf input/output capacitance, dq 0 to dq 63 c dq 20 pf
6 mb8502e064ab-60/-70 n recommended operating conditions (referenced to v ss ) * : undershoots of up to e1.5 volts with a pulse width not exceeding 10 ns are acceptable. n dc characteristics (at recommended operating conditions unless otherwise noted.) notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rate. the specitc values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih , v il > e0.3 v. i cc1 , i cc3 , i cc4 and i cc5 are specited at one time of address change during ras = v il and cas = v ih . parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v ground v ss ?0?v input high voltage, all inputs v ih 2.4 ? 6.0 v input low voltage, all inputs* v il e0.3 ? 0.8 v ambient temperature t a 0?70 c parameter notes symbol condition value unit min. max. output high voltage *1 v oh i oh = e5.0 ma 2.4 ? v output low voltage *1 v ol i ol = +4.2 ma ? 0.4 v input leakage current ras i i(l) 0 v v in 5.5 v, 4.5 v v cc 5.5 v, v ss = 0 v, all other pins not under test = 0 v 30 m a others e10 10 output leakage current i o(l) 0 v v out 5.5 v, 4.5 v v cc 5.5 v, data out disabled e10 10 m a operating current (average power supply current) *2 mb8502e064ab-60 i cc1 ras & cas cycling, t rc = min 1200 ma MB8502E064AB-70 1110 standby current (power supply current) *2 ttl level i cc2 ras = cas = pde = v ih 80 ma cmos level ras = cas = pde 3 v cc e0.2 v 69 refresh current #1 (average power supply current) *2 mb8502e064ab-60 i cc3 cas = v ih , ras = cycling, t rc = min 1200 ma MB8502E064AB-70 1110 hyper page mode current *2 mb8502e064ab-60 i cc4 ras = v il , cas = cycling, t hpc = min 1200 ma MB8502E064AB-70 1110 refresh current #2 (average power supply current) *2 mb8502e064ab-60 i cc5 ras = cycling, cas -before- ras , t rc = min 1120 ma MB8502E064AB-70 1030 refresh current #3 (average power supply current) i cc9 self refresh; a 0 to a 10 , b 0 , we , oe , pde 3 v cc e2.1 v 30 ma e30 ? ? ? ? ? ? ? ? ? ? ?
7 mb8502e064ab-60/-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 no. parameter notes symbol mb8502e064ab-60 MB8502E064AB-70 unit min. max. min. max. 1 time between refresh t ref ? 32.8 ? 32.8 ms 2 random read/write cycle time t rc 104 ? 124 ? ns 3 read-modify-write cycle time t rwc 138 ? 162 ? ns 4 access time from ras *4,7 t rac ? 60 ? 70 ns 5 access time from cas *5,7 t cac ? 20 ? 22 ns 6 column address access time *6,7 t aa ? 35 ? 40 ns 7 output hold time t oh 5?5?ns 8 output hold time from cas t ohc 77ns 9 output buffer turn on delay time t on 2?2?ns 10 output buffer turn off delay time *8 t off ? 20 ? 22 ns 11 output buffer turn off delay time from ras *8 t ofr ? 15 ? 17 ns 12 output buffer turn off delay time from we *8 t wez ? 20 ? 22 ns 13 transition time t t 1 16 1 16 ns 14 ras precharge time t rp 40 ? 50 ? ns 15 ras pulse width t ras 60 100000 70 100000 ns 16 ras hold time t rsh 20 ? 22 ? ns 17 cas to ras precharge time t crp 5?5?ns 18 ras to cas delay time *9,10 t rcd 12 45 12 53 ns 19 cas pulse width t cas 10 ? 13 ? ns 20 cas hold time t csh 38 ? 48 ? ns 21 cas precharge time (normal) *17 t cpn 10 ? 10 ? ns 22 row address set up time t asr 5?5?ns 23 row address hold time t rah 8?8?ns 24 column address set up time t asc 0?0?ns 25 column address hold time t cah 10 ? 10 ? ns 26 column address hold time from ras t ar 22 ? 22 ? ns 27 ras to column address delay time *11 t rad 10 35 10 40 ns 28 column address to ras lead time t ral 35 ? 40 ? ns 29 column address to cas lead time t cal 23 ? 28 ? ns 30 read command set up time t rcs 5?5?ns
8 mb8502e064ab-60/-70 (continued) no. parameter notes symbol mb8502e064ab-60 MB8502E064AB-70 unit min. max. min. max. 31 read command hold time referenced to ras *12 t rrh e2 ? e2 ? ns 32 read command hold time referenced to cas *12 t rch 0?0?ns 33 write command set up time *13,18 t wcs 0?0?ns 34 write command hold time t wch 10 ? 10 ? ns 35 write command hold time from ras t wcr 22 ? 22 ? ns 36 we pulse width t wp 8?8?ns 37 write command to ras lead time t rwl 20 ? 22 ? ns 38 write command to cas lead time t cwl 10 ? 13 ? ns 39 din set up time t ds e2 ? e2 ? ns 40 din hold time t dh 15 ? 15 ? ns 41 data hold time from ras t dhr 24 ? 24 ? ns 42 ras to we delay time *18 t rwd 75 ? 87 ? ns 43 cas to we delay time *18 t cwd 32 ? 36 ? ns 44 column address to we delay time *18 t awd 47 ? 54 ? ns 45 ras precharge time to cas active time (refresh cycles) t rpc 3?3?ns 46 cas set up time (c-b-r refresh) t csr 5?5?ns 47 cas hold time (c-b-r refresh) t chr 12 ? 14 ? ns 48 access time from oe *7 t oea ? 20 ? 22 ns 49 output buffer turn off delay from oe *8 t wcz ? 20 ? 22 ns 50 oe to ras lead time for valid data t wcl 15 ? 15 ? ns 51 oe to cas lead time t col 5?5?ns 52 oe hold time referenced to we *14 t oeh 5?5?ns 53 oe to data in delay time t oed 20 ? 22 ? ns 54 ras to data in delay time t rdd 15 ? 15 ? ns 55 cas to data in delay time t cdd 20 ? 22 ? ns 56 din to cas delay time *15 t dzc e2 ? e2 ? ns 57 din to oe delay time *15 t dzo e2 ? e2 ? ns 58 oe precharge time t oep 8?8?ns 59 we hold time referenced to cas t oech 10 ? 10 ? ns 60 we precharge time t wpz 8?8?ns
9 mb8502e064ab-60/-70 (continued) no. parameter notes symbol mb8502e064ab-60 MB8502E064AB-70 unit min. max. min. max. 61 we to data in delay time t wed 20 ? 22 ? ns 62 hyper page mode ras pulse width t rasp ? 100000 ? 200000 ns 63 hyper page mode read/write cycle time t hpc 25 ? 30 ? ns 64 hyper page mode read-modify- write cycle time t hprwc 69 ? 79 ? ns 65 access time from cas precharge *7,16 t cpa ? 40 ? 45 ns 66 hyper page mode cas precharge time t cp 10 ? 10 ? ns 67 hyper page mode ras hold time from cas precharge t rhcp 40 ? 45 ? ns 68 hyper page mode cas precharge to we delay time *18 t cpwd 52 ? 59 ? ns 69 ras pulse width (self refresh) *19 t rass 100 ? 100 ? m s 70 ras precharge time (self refresh) *19 t rps 104 ? 124 ? ns 71 cas hold time (self refresh) *19 t chs e52 ? e52 ? ns
10 mb8502e064ab-60/-70 notes: *1. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. if an internal refresh counter is used, a minimum of eight cas - before-ras initialization cycles are required instead of eight ras cycles. *2. ac characteristics assume t t = 5 ns. *3. v ih (min) and v il (max) are reference levels for measureing the timing of input signals. transition times are measured between v ih (min) and v il (max). *4. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. *5. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *6. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *7. measured with a load equivalent to two ttl loads and 100 pf. *8. t off , t oez , t ofr and t wez is specited that output buffer change to high-impedance state. *9. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specited as a reference point only; if t rcd is greater than the specited t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *10. t rcd (min) = t rah (min) + 2 t t + t asc (min). *11. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is specited as a reference point only; if t rad is greater than the specited t rad (max) limit, access time is controlled exclusively by t cac or t aa . *12. either t rrh or t rch must be satisted for a read cycle. *13. t wcs is specited as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *14. assumes that t wcs < t wcs (min). *15. either t dzc or t dzo must be satisted. *16. t cpa is access time from the selection of a new column address (caused by changing cas from l to h). therefore, if t cp become long, t cpa also become longer than t cpa (max). *17. assumes that cas -before-ras refresh. *18. t wcs , t cwd , t rwd , t awd , and t cpwd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs 3 t wcs (min), the cycle is an early write cycle and d out pin will maintain high-impedance state thoughout the entire cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min), and t cpwd 3 t cpwd (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satisted, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , t ral and t cal specitcations. *19. assumes that self refresh. *source: see mb8117805a data sheet for details on the electricals.
11 mb8502e064ab-60/-70 n package dimensions (suftx: dg) c 1996 fujitsu limited m168006sc-1-1 84 1 85 168 65.680.13(2.586.005) 66.680.13(2.625.005) c l 131.350.13(5.171.005) 133.350.13(5.250.005) 4.000.13 (.157.005) ?3.000.05 (?.118.002) 3.000.13 (.118.005) 25.400.13 (1.000.005) 3.170.13 (.125.005) 36.830.05 (1.450.002) 43.180.13(1.700.005) 63.680.13(2.507.005) 11.430.05 (.450.005) c l 1.270.03 (.050.001) 54.610.05(2.150.002) 115.570.13(4.550.005) 127.350.10(5.014.004) pin no.1 index. .050 ?.003 +.004 ?0.08 +0.10 1.27 17.780.13 (.700.005) notches full r "a" "b" "c" 1.000.05 (.039.002) details of "c" part 3.25(.128) 3.00(.118) c l 2.54(.100)typ. 0.25(.010)max. details of "b" part 4.00(.157)min. 2.000.10(.079.004) 1.000.05(.039.002) 6.350.13 (.250.005) 3.25(.128) 3.00(.118) 2.000.10(.079.004) 6.350.13(.250.005) 1.000.05(.039.002) details of "a" part 8.89(.350)max. 3.00(.118)min. dimensions in mm(inches). 168 pin, plastic dimm (mds-168p-p06)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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